1. Field of the Invention
Embodiments of the invention are related to a semiconductor device and a method of manufacturing a semiconductor device.
2. Description of the Related Art
In a conventional vertical metal oxide semiconductor field effect transistor (MOSFET) that is a switching device using silicon carbide (SiC), a silicon carbide layer of a first conductivity type and having a low impurity concentration is formed on a surface of a silicon carbide substrate of the first conductivity type. A gate structure and a source structure are formed on a surface side of the silicon carbide layer, and a drain structure is formed on a first side of the silicon carbide substrate opposite a second side having the silicon carbide layer. The source structure is surrounded by a base region of a second conductivity type and a source electrode is bonded to the base region and a source region of the first conductivity type.
In a vertical MOSFET, when breakdown occurs during high voltage operation, a large current flows. By the occurrence of breakdown in an active region having an area larger than an edge termination region surrounding an active region in which an element structure is formed and through which current flows in the ON state, the vertical MOSFET reduces the absorption energy per unit area thereby increases tolerance. For such reasons, in general, a structure is designed enabling breakdown to occur easily in the active region. In the active region, a corner portion (e.g., reference numeral 201 in FIG. 1 and reference numeral 202 in FIG. 6 described hereinafter) of a base region in a Junction FET (JFET) region is formed whereby high electric field tends to be applied to this corner portion and when breakdown occurs, current flows from the drain and passes through a corner of the base region to the source electrode. As a result, a voltage decrease due to the current flowing in a base layer causes the potential of the base layer to decrease whereby a parasitic transistor formed by a source layer of the first conductivity type, a base layer of the second conductivity type and a substrate of the first conductivity type turns ON and may lead to element destruction.
To resolve such problems, according to one technique, on at least a lower side of the source region in the base region, a region having a high oxygen (O2) concentration is provided whereby base current of a parasitic transistor formed by a source region, a base region and an epitaxial layer is blocked, suppressing operation (turn ON) of the parasitic transistor (e.g., refer to Japanese Laid-Open Patent Publication No. H05-55594). According to a further technique, below a contact region in an n-type drift layer, an n+-type region is formed so as to be apart from a p-type base region whereby operation of a parasitic transistor is suppressed, enabling tolerance to be improved (e.g., refer to Japanese Laid-Open Patent Publication No. 2009-94203).